The present invention is related in general to integrated circuits (ICs), and more particularly to an apparatus for power management circuits having data retention.
Many portable electronic devices such as cellular phones, digital cameras/camcorders, personal entertainment devices, laptop or palmtop computers, and video games operate on batteries. During periods of inactivity or reduced activity the device may not perform processing operations and the device or selectable portions thereof may be placed in one of a plurality of power saving (or power reduction) modes of operation. Typical power saving modes may include a power-down mode, a standby power mode, and an active power saving (or idle state low power mode). The device operating in an active mode of operation (e.g., mode in which the device is fully functional consuming rated power) may detect a slightly higher idle time compared to a reference. A power management circuit (PMC) may detect the higher idle time and may place the device in the active power saving mode until the idle time is equal to or below the reference. A typical duration for which the device (or a portion thereof) may be placed in the power-down mode, the standby power mode, and the active power saving mode may respectively vary from several hours or days for the power-down mode, to several minutes or hours for the or standby power mode, and to a few or several clock cycles for the active power saving mode.
It is well known that various circuits within the electronic device may be partitioned into multiple logic circuit domains that may be powered by corresponding power domains. The power domains may be selectively controlled in the various power saving modes of operation to reduce power consumption. Traditional data retention circuits such as flip flops or latches within the device may be used to store status information for later use prior to the circuit or the device entering the power saving mode. The data retention latch, which may also be referred to as a shadow latch or a balloon latch, is typically powered by a separate ‘always on’ power supply. However, restoration of the retained status information for devices operating in an active power saving mode in a timely manner, e.g., without any clock latency, represents a challenge for designing portable devices having an extended battery life. In addition, presence of leakage current during the active power saving mode also reduce the battery life.